1. Field of the Invention
The present invention relates generally to sense amplifiers and, more particularly, to secondary sense amplifier devices which include a window discriminator which enables the device to read data without the need for the device to be externally triggered.
2. Description of the Prior Art
Electronic memory devices such as Dynamic Random Access Memory (DRAM) devices or Static Random Access Memory (SRAM) devices are utilized in various electronic systems for storing large amounts of digitally encoded information. These devices typically include memory arrays which are utilized to store the digitally encoded information or data. The data is typically retrieved from such memory arrays by a device known as a sensing system.
As shown in FIG. 1, a typical sensing system 10 in a DRAM device very often consists of a primary sense amplifier 12 and a secondary sense amplifier 14. The primary sense amplifier 12 is typically utilized to directly read data from the memory array, while the secondary sense amplifier 14 is typically utilized to read the data from the primary sense amplifier 12. This two part configuration is necessary in order to meet the high density requirements of DRAM devices. This is because DRAM devices contain a much larger number of primary sense amplifiers than secondary sense amplifiers, wherein these primary sense amplifiers are fabricated from transistors having a relatively small size which may be implemented in a high density array. Data is transferred between the sense amplifiers 12,14 through a pair of high capacitance lines respectively known as external bit line true (EBLt) 16 and external bit line complement (EBLc) 18.
During a read cycle, the primary sense amplifier 12 reads data from the memory array (not shown). The data is stored temporarily within the primary sense amplifier 12 by utilizing a latch. In order to transfer this stored data, the external bit lines 16,18 have to be pre-charged to a predetermined positive voltage before being coupled to the latch within the primary sense amplifier 12. The pre-charging is necessary in order to prevent the high capacitance external bit lines 16,18 from overriding the voltages stored within the primary sense amplifier 12. Such an overriding condition is possible because of the relative small size of the transistors utilized in the primary sense amplifier 12.
When the external bit lines 16,18 are then coupled to the latch within the primary sense amplifier 12, the voltage on one of the lines 16,18 drops below the pre-charge level which causes a differential voltage to develop. The respective condition associated with each of the external bit lines dropping below the pre-charge level ,thus providing two possible polarities of the differential voltage present across the external bit lines 16,18, represents the two logic states of the data stored in the primary sense amplifier 12. This differential voltage is then sensed by the secondary sense amplifier 14 in order to appropriately drive the read data lines (RDL). The data is read by another latch included in the secondary sense amplifier 14 which is set to one of the two possible logic states according to the polarity of the differential voltage.
Referring now to FIG. 2, an example of a conventional secondary sense amplifier is shown. The secondary sense amplifier 20 includes a latch 22 which includes a pair of cross-coupled inverters 24, 26. Each inverter 24, 26 includes a p-channel field effect transistor (FET) 24A and 26A and an n-channel FET 24B, 26B. The cross-coupling is accomplished by coupling the output of each inverter to the input of the other inverter. Nodes A and B are respectively formed at the junctions of the cross coupling. Such configuration enables the latch 22 to have two steady states, for instance, node A being a logic high and node B being a logic low, or vice versa. The latch 22 is considered to be in one of the two possible logic states when it is being driven towards either steady state condition. Nodes A and B of the latch 22 are respectively coupled to the external bit lines EBLt and EBLc at terminals 32, 34. As previously discussed, a differential voltage is developed across these external bit lines which subsequently determines the respective states of nodes A and B.
An n-channel FET 28 is coupled to the drains of the n-channel FETs 24B, 26B and is utilized to trigger the latch 22. The triggering transistor 28 is utilized to effectively isolate the latch 22 from the differential voltage developed across the external bit lines EBLt and EBLc for a predetermined amount of time. Such isolation is necessary in order to permit the differential voltage to reach a significant magnitude such that the differential voltage is capable of setting the latch 22 to one of its logic states. The necessary magnitude is typically about 200 millivolts (mV) which takes about 2 nanoseconds (nsec) to develop across the external bit lines which, themselves, each have a capacitance of about 2 picofarads (pF).
However, due to noise and offset considerations, the magnitude required to set the latch 22 is actually higher, for instance, in the range between about 200 to about 500 mV. For the differential voltage across the external bit lines to attain this magnitude, an additional 1 to 2 nsec is typically required. Thus, the triggering transistor 28 is turned on by a set signal about 3 to 4 nsec after the external bit lines are coupled to the primary sense amplifier, wherein about 1 to 2 nsec is a built-in margin to account for any noise or offsets. Accordingly, as is known, this 1 to 2 nsec serves as a safety guard band and also accounts for mismatch in column select line (CSL) drivetime, signal development time, as well as other timing mismatches known to occur in such devices.
Further, two pre-charge transistors 30, 32 are coupled between the inverter nodes A,B and voltage source VDD. These transistors 30, 32 are utilized to pre-charge the external bit lines (in response to the application of signal PC to their respective gate terminals), and thus the inverter nodes A,B, to the supply voltage VDD in order to prevent overriding, as previously discussed. The inverter nodes A,B are pre-charged in order to indicate to the rest of the memory device that the secondary sense amplifier does not contain data and thus enables the latch 22 to be driven to one of its logic states.
Referring now to FIG. 3, a diagram of the operational states of a typical latch, such as latch 22, included in a conventional secondary sense amplifier is shown. The x and y axis respectively represent the voltage levels of the inverter nodes A and B. A meta-stable line 38 represents the semi-stable states of the latch which include the pre-charge state 44, where nodes A and B equal VDD. Due to device irregularities, this meta-stable line may actually be located anywhere between the dashed lines 38A, 38B shown on either side of line 38. The previously discussed two stable states of the latch are designated by reference numerals 40 and 42.
The respective areas C and D between the meta-stable line 38 and the two stable states 40 and 42 represent the two possible logic states of the latch. As previously discussed in regard to FIG. 2, the latch is first driven into its pre-charge state by the PC signal turning on the pre-charge transistors 30, 32. Then, when a sufficient differential voltage is developed across the high capacitive external bit lines, the set signal turns on the triggering transistor 28. This causes the latch 22 to be driven towards one of its stable states 40 or 42, thereby setting the latch to one of its two possible logic states. In DRAM devices (particularly, asynchronous DRAM devices), the set signal is usually developed by an address transition detect (ATD) block.
The need for a conventional secondary sense amplifier, such as secondary sense amplifier 20, to be triggered by an external set signal has a number of disadvantages. First of all, a memory device utilizing such a scheme is larger in size since additional components are required to generate the set signal. Also, the power consumed by such a memory device is considerably higher. This is because the set signal utilized may need to be driven over a long signal line thus requiring the set signal to be a relatively large amplitude signal, which requires a considerable amount of power to generate. Also, such a memory device is inherently slower due to the built-in margin requirements discussed above.